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Electronics 15 min read

How to Choose a Pull-Up Resistor Value (With I2C Math)

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Cinematic poster of an astronaut soldering a circuit board inside a sealed glove bag on the space station, with the title "Pick A Pull-Up" in large condensed type and the line "Fast edges or low current.".
#Electronics #I2C #Resistors #Microcontrollers

4.7 kΩ is probably the most copied number in hobby electronics. It is on breakout boards, in tutorials and in half the I²C schematics on the internet. Run the arithmetic from the I²C specification and you find that at 400 kHz, a 4.7 kΩ pull-up meets the rise-time limit only while the bus capacitance stays below 75 pF. Add a 30 cm ribbon cable and a few sensors and you are past it. The bus usually keeps working anyway, which is exactly why the number survives.

This post shows where pull-up values actually come from: a lower bound, an upper bound, and a calculation that tells you which side of the window you are on. The same reasoning covers buttons and plain GPIO inputs, where the numbers are far more forgiving.

Quick answerA pull-up must be large enough that the driver can pull the line low (Rmin⁡=(VDD−VOL)/IOLR_{\min} = (V_{DD} - V_{OL})/I_{OL}) and small enough to charge the line capacitance in time (Rmax⁡=tr/(0.8473 Cb)R_{\max} = t_r/(0.8473\,C_b) for I²C). For 3.3 V I²C at 400 kHz on a 200 pF bus, that window is 970 Ω to 1.77 kΩ: use 1.5 kΩ.
Infographic: How do you choose a pull-up resistor value? An I²C bus drawing shows a pull-up resistor, three devices and a slow RC rising edge. Headline: the common 4.7 kΩ meets the 400 kHz rise-time limit only up to about 75 pF of bus capacitance. 1.5 kΩ suits a 200 pF bus, and 967 ohms is the minimum on a 3.3 V bus. A log chart of resistance against bus capacitance shows the maximum falling for 100 kHz and 400 kHz while the 3 mA minimum stays flat; the 400 kHz window closes at 366 pF. Tiles: rise time is 0.8473 RC, 20 to 50 kΩ internal pull-ups are too weak, 10 kΩ suits buttons.
Tap the image to view it full size. View the accessible, editable SVG.

What does a pull-up resistor actually do?

A pull-up gives a line a defined HIGH level when nothing is actively driving it. That matters in two situations. An input pin connected to a button floats when the button is open, and a floating CMOS input drifts with stray fields. And open-drain buses such as I²C are built so that every device can only pull the line LOW; nobody drives it HIGH. The resistor is the only thing that brings it back up.

Schematic of an I2C bus: SDA and SCL lines each connected to a 3.3 volt supply through a pull-up resistor Rp, a controller and two target devices each with open-drain switches to ground on both lines, and a capacitor Cb from the line to ground representing bus capacitance.
Figure 1. An I²C bus. Each device can only connect a line to ground. When all of them let go, the pull-up resistor Rp charges the line's total capacitance Cb (traces, cable and up to 10 pF per device pin) back toward VDD.

That second job is why pull-up value matters on buses. Pulling the line low is fast, because a transistor does it with tens of milliamps of drive. Letting it go high is slow, because the only current available is what flows through Rp. The rising edge is an RC charging curve, and the time constant is set by your resistor.

Why is there a minimum pull-up value?

When a device pulls the line low, it has to sink the current flowing down through the pull-up. If Rp is too small, that current exceeds what the output transistor can sink while staying near 0 V, and the LOW level climbs. NXP's I²C specification (UM10204) guarantees that Standard-mode and Fast-mode outputs can sink 3 mA with VOL no higher than 0.4 V. Fast-mode Plus parts are guaranteed 20 mA.

Minimum pull-up, Standard and Fast mode

Rp(min⁡)=VDD−VOL(max⁡)IOLR_{p(\min)} = \frac{V_{DD} - V_{OL(\max)}}{I_{OL}}
3.3 V: 3.3−0.40.003=967 Ω5.0 V: 5.0−0.40.003=1533 Ω5.5 V: 5.5−0.40.003=1.7 kΩFm+, 3.3 V: 3.3−0.40.020=145 Ω\begin{aligned}3.3\ \mathrm{V}:&\ \tfrac{3.3 - 0.4}{0.003} = \mathbf{967\ \Omega} \\ 5.0\ \mathrm{V}:&\ \tfrac{5.0 - 0.4}{0.003} = 1533\ \Omega \\ 5.5\ \mathrm{V}:&\ \tfrac{5.5 - 0.4}{0.003} = 1.7\ \mathrm{k\Omega} \\ \text{Fm+, }3.3\ \mathrm{V}:&\ \tfrac{3.3 - 0.4}{0.020} = 145\ \Omega\end{aligned}

5.5 V is the worst case (5 V + 10%) and the spec's own example.

Go below this and nothing explodes. What happens is quieter: the LOW level might sit at 0.6 or 0.8 V instead of 0.4 V, eating into the 0.3 VDD threshold (0.99 V at 3.3 V) that receivers use to recognize a zero. Add ground bounce and a weak driver at high temperature and you get the occasional corrupted byte that nobody can reproduce on the bench.

Why is there a maximum pull-up value?

There are two upper limits, and on I²C the first one almost always wins.

The rise-time limit, and where 0.8473 comes from

When the line is released, it charges as V(t)=VDD(1−e−t/RC)V(t) = V_{DD}(1 - e^{-t/RC}). I²C defines rise time between the 30% and 70% levels, because those are the input thresholds VIL and VIH. Solve for each crossing:

0.3VDD: t1=−RCln⁡0.7=0.3567 RC0.7VDD: t2=−RCln⁡0.3=1.2040 RCtr=t2−t1=0.8473 RC\begin{aligned}0.3V_{DD}:\ t_1 &= -RC\ln 0.7 = 0.3567\,RC \\ 0.7V_{DD}:\ t_2 &= -RC\ln 0.3 = 1.2040\,RC \\ t_r &= t_2 - t_1 = \mathbf{0.8473\,RC}\end{aligned}

So:

Rp(max⁡)=tr(max⁡)0.8473 CbR_{p(\max)} = \frac{t_{r(\max)}}{0.8473\,C_b}

tr(max) is 1000 ns for Standard-mode (100 kHz), 300 ns for Fast-mode (400 kHz) and 120 ns for Fast-mode Plus (1 MHz).

A common misconception is that rise time "is" RC, or the 10% to 90% time of 2.2 RC that you learn for oscilloscopes. Use either for I²C and you will be wrong by a factor of 1.2 or 2.6. The 0.8473 factor is in UM10204 itself, derived exactly as above.

Line voltage versus time after release for 1.5, 4.7 and 10 kilohm pull-ups on a 200 picofarad bus at 3.3 volts, with dashed thresholds at 0.99 and 2.31 volts. The 1.5 kilohm curve has a 254 nanosecond rise time, 4.7 kilohm 797 nanoseconds and 10 kilohm 1695 nanoseconds.
Figure 2. Rising edges on a 200 pF bus, computed from the RC charging equation. The shaded strip shows the 300 ns Fast-mode budget for scale. Only 1.5 kΩ meets it; 4.7 kΩ takes 797 ns and 10 kΩ takes 1.7 µs, more than half of a 2.5 µs clock period at 400 kHz.

The leakage limit

Every input on the bus leaks a little current, up to 10 µA per pin in the I²C specification. That current flows through Rp and drags the HIGH level down. UM10204 asks for a HIGH-level noise margin of 0.2 VDD:

Rp(max⁡, leak)=0.2 VDDN×10 μAR_{p(\max,\,\mathrm{leak})} = \frac{0.2\,V_{DD}}{N \times 10\ \mu\mathrm{A}}

3.3 V bus with 5 devices:

0.66 V/50 μA=13.2 kΩ0.66\ \mathrm{V}/50\ \mu\mathrm{A} = \mathbf{13.2\ k\Omega}

This bound is real but rarely the one that bites, since the rise-time limit is usually much lower. It matters on slow buses with many devices, and on general-purpose inputs where rise time does not matter at all.

Worked example: 3.3 V I²C at 400 kHz with a 200 pF bus

Say you have a controller, four sensors and a 40 cm cable to a second board. You measured or estimated 200 pF of total capacitance on each line (more on estimating below).

Step 1. Lower bound (sink current)

Rmin⁡=(3.3−0.4) V/3 mA=967 ΩR_{\min} = (3.3 - 0.4)\ \mathrm{V}/3\ \mathrm{mA} = 967\ \Omega

Step 2. Upper bound (rise time)

Rmax⁡=300 ns0.8473×200 pF=300×10−91.695×10−10=1770 Ω\begin{aligned}R_{\max} &= \frac{300\ \mathrm{ns}}{0.8473 \times 200\ \mathrm{pF}} \\ &= \frac{300{\times}10^{-9}}{1.695{\times}10^{-10}} = 1770\ \Omega\end{aligned}

Step 3. Upper bound (leakage, 6 pins)

0.66 V/60 μA=11 kΩ0.66\ \mathrm{V}/60\ \mu\mathrm{A} = 11\ \mathrm{k\Omega}

Not limiting.

Step 4. Pick a standard value inside 967 Ω to 1,770 Ω

1.5 kΩ (E12) gives a 15% margin on rise time, a sink current inside 3 mA, and this supply current while a line is LOW:

tr=0.8473×1500×200 p=254 nsIsink=(3.3−0.4)/1500=1.9 mAIsupply=3.3/1500=2.2 mA\begin{aligned}t_r &= 0.8473 \times 1500 \times 200\,\mathrm{p} = \mathbf{254\ ns} \\ I_{\mathrm{sink}} &= (3.3 - 0.4)/1500 = 1.9\ \mathrm{mA} \\ I_{\mathrm{supply}} &= 3.3/1500 = 2.2\ \mathrm{mA}\end{aligned}

The window is narrow: less than a factor of two. Figure 3 shows why. As the bus capacitance grows, the maximum falls until it crosses the minimum, and past that point no resistor will do.

Log-scale plot of pull-up resistance versus bus capacitance from 10 to 550 picofarads. Curves show maximum resistance for Standard-mode, Fast-mode and Fast-mode Plus; a horizontal dashed line marks the 0.97 kilohm minimum at 3.3 volts. The shaded Fast-mode window closes near 366 picofarads. A dot marks the 1.5 kilohm, 200 picofarad worked example, and a ring marks 4.7 kilohms at 75 picofarads.
Figure 3. The allowed pull-up window versus bus capacitance at 3.3 V. Upper curves: Rmax⁡=tr/(0.8473 Cb)R_{\max} = t_r/(0.8473\,C_b). Dashed lines: Rmin from the guaranteed sink current (3 mA, or 20 mA for Fast-mode Plus). The Fast-mode window closes at about 366 pF, below the 400 pF that the spec allows.

That closing point is worth a second look. Plug Rmin = 967 Ω into the rise-time equation and you get Cmax⁡=300 ns/(0.8473×967)=366 pFC_{\max} = 300\ \mathrm{ns}/(0.8473 \times 967) = 366\ \mathrm{pF}. On a 3.3 V bus with plain 3 mA devices, you cannot actually use the full 400 pF that Fast mode permits. The spec itself flags this: its footnote says full bus load at 400 kHz needs 6 mA of sink current at VOL = 0.6 V. For bigger buses, the fixes are Fast-mode Plus drivers, a bus buffer that splits the capacitance, or a switched (active) pull-up circuit, all described in UM10204.

Is a smaller pull-up always safer?

This is the second misconception, and it comes from people who were burned by slow edges. Lower resistance does give faster edges and better noise immunity. But below Rmin you trade a visible problem (slow edges) for an invisible one (LOW levels creeping toward the threshold), and you pay in power the whole time. On a battery sensor that holds SDA low for half of every transfer, 1 kΩ at 3.3 V costs 3.3 mA per line while low, while 4.7 kΩ costs 0.7 mA. NXP's own advice is that portable designs should sit toward the high end of the window to save supply current. The goal is to land inside the window, not at one wall of it.

How do you estimate bus capacitance?

You need Cb for the calculation, and it is the number most people skip. Two practical approaches:

  • Add it up. The I²C specification allows each device pin up to 10 pF. Add the PCB traces (a typical trace over a ground plane is on the order of 1 pF per centimetre, depending on geometry) and any cable, which typically adds something like 50 to 100 pF per metre. Then add 20 to 30% margin for things you forgot, like a logic analyser probe.
  • Measure it. This is the better option and takes two minutes. Fit any pull-up, put a scope on SDA, and time the edge from 30% to 70% of VDD. Then Cb = tr / (0.8473 Rp). With a 4.7 kΩ pull-up and a measured 400 ns rise time, Cb = 400 ns / (0.8473 × 4,700) = 100 pF. Use a 10x probe; a 1x probe adds its own 50 pF or more.

When are internal MCU pull-ups too weak?

Most microcontrollers have pull-ups you can enable in software, and they are deliberately weak to save current. The ATmega328P (Arduino Uno) specifies 20 to 50 kΩ. The RP2040 (Raspberry Pi Pico) specifies 50 to 80 kΩ. Figure 4 shows what those values mean for I²C.

Horizontal bar chart on a log scale of the largest bus capacitance each pull-up value can drive within I2C rise-time limits. At 100 kilohertz: 1.5 kilohms 787 picofarads, 4.7 kilohms 251, 10 kilohms 118, 50 kilohms 24, 80 kilohms 15. At 400 kilohertz: 236, 75, 35, 7 and 4 picofarads. A shaded band marks values below 10 picofarads, the capacitance of a single pin.
Figure 4. Largest bus capacitance each pull-up can drive within the I²C rise-time limits, from Cmax⁡=tr/(0.8473 R)C_{\max} = t_r/(0.8473\,R). Internal pull-ups at 400 kHz cannot even charge one 10 pF pin in time. At 100 kHz a 20 kΩ internal pull-up manages 59 pF, which is one short, lucky bus.

So internal pull-ups are the wrong tool for I²C, with one honest exception: very short, slow buses where the rise time violates the spec but the receiver still sees a clean level before the clock samples it. That "works on my desk" case is where most of the folklore about internal pull-ups comes from. It is not a design, it is a coincidence.

Where internal pull-ups are perfectly good: buttons, jumpers, DIP switches and other inputs that change at human speed and sit right next to the chip.

Pull-ups for buttons and plain GPIO inputs

Without a rise-time deadline, the window for a button is enormous. The bounds become:

Upper bound: leakage (ATmega328P at 5 V)

Input leakage IIH is at most 1 µA, and the pin is guaranteed HIGH above VIH=0.6 VCC=3.0 VV_{IH} = 0.6\,V_{CC} = 3.0\ \mathrm{V}:

Rmax⁡=(5.0−3.0)/1 μA=2 MΩR_{\max} = (5.0 - 3.0)/1\ \mu\mathrm{A} = 2\ \mathrm{M\Omega}

Lower bound: current while pressed

10 kΩ at 3.3 V: 330 μA1 kΩ at 3.3 V: 3.3 mA\begin{aligned}10\ \mathrm{k\Omega}\text{ at }3.3\ \mathrm{V}&:\ 330\ \mu\mathrm{A} \\ 1\ \mathrm{k\Omega}\text{ at }3.3\ \mathrm{V}&:\ 3.3\ \mathrm{mA}\end{aligned}

3.3 mA is wasteful for a button held down.

Nobody should use 2 MΩ, though. A high-impedance node acts as an antenna, and dust, flux residue and humidity on the board can leak far more than the chip's 1 µA. The practical range is roughly 4.7 kΩ to 47 kΩ, and 10 kΩ is a fine default. Go stronger (1 to 4.7 kΩ) when the button sits at the end of a long cable in an electrically noisy box, because a lower impedance makes induced noise currents produce smaller voltages. Pair it with a small capacitor for debouncing and EMI filtering if needed.

The procedure in four lines: (1) find the sink current IOL at VOL for the weakest driver and compute Rmin; (2) estimate or measure Cb and compute Rmax from your rise-time budget; (3) check leakage for slow, many-device buses; (4) pick a standard value inside the window, nearer the top if you care about power and nearer the bottom if you care about noise.

FAQ

What value pull-up resistor should I use for I2C?

Compute a window. The minimum is (VDD minus 0.4 V) divided by 3 mA, about 970 Ω at 3.3 V. The maximum is the rise-time limit divided by 0.8473 times the bus capacitance: 300 ns for 400 kHz, 1000 ns for 100 kHz. For a 200 pF bus at 400 kHz that gives 1.77 kΩ, so 1.5 kΩ is a good choice.

Is 10k too high for an I2C pull-up?

Usually, yes. A 10 kΩ pull-up meets the 400 kHz rise-time limit only if the total bus capacitance is below about 35 pF, and the 100 kHz limit only below about 118 pF. It can work on a tiny board with one or two devices, but it leaves little margin.

Can I use the microcontroller’s internal pull-ups for I2C?

Rarely. Internal pull-ups are typically 20 to 80 kΩ (20 to 50 on an ATmega328P, 50 to 80 on an RP2040). At 50 kΩ the Standard-mode rise-time limit allows only about 24 pF of bus capacitance, which a couple of chips and a short cable already exceed. Use external resistors.

What happens if a pull-up resistor is too small?

The driver pulling the line low has to sink more current than it is guaranteed to handle, so the LOW voltage rises and may no longer be read as a logic 0. It also wastes power whenever the line is low. For I²C, devices are only guaranteed to sink 3 mA at 0.4 V in Standard and Fast mode.

What pull-up resistor value should I use for a button?

Anything from about 4.7 kΩ to 47 kΩ works for a button next to the microcontroller; 10 kΩ is a sensible default. Speed is irrelevant for a human press, so the choice trades current while pressed (330 µA at 3.3 V with 10 kΩ) against noise pickup on long wires.

Sources

  1. NXP Semiconductors, UM10204 I²C-bus specification and user manual, Rev. 7.0 (2021): Table 10 (VOL, IOL, tr, Cb, Ci, Ii), Section 7.1 pull-up sizing and the 0.8473 RC derivation, Section 7.4 input leakage: nxp.com/docs/en/user-guide/UM10204.pdf
  2. Texas Instruments, SLVA689 "I2C Bus Pullup Resistor Calculation" (R. Arora, 2015): ti.com/lit/SLVA689
  3. Microchip (Atmel), ATmega328P automotive datasheet 7810D, Section 28.2 DC characteristics (RPU 20 to 50 kΩ, IIH 1 µA, VIH 0.6 VCC): ww1.microchip.com ATmega328P datasheet PDF
  4. Raspberry Pi Ltd, RP2040 datasheet, GPIO electrical specifications (pull-up resistance 50 to 80 kΩ): datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf

All curves in this post are computed from the equations shown, using the limits in UM10204 Rev. 7.0. PCB trace and cable capacitance figures are typical orders of magnitude; measure your own bus when it matters.

Header image: NASA/ESA (Sophie Adenot) (image iss075e0103086), regraded for this article.

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