Logic Gate Symbols and Truth Tables (Printable Chart) • The Science 360

A 74HC00 chip costs less than a cup of tea, holds four NAND gates and switches each one in about 9 nanoseconds. Five chips from the same family (two XOR, two AND and one OR) are enough to add two 4-bit numbers. Every phone processor does the same job with billions of gates instead of sixteen, but the rules each gate follows have not changed since the 1960s, and there are only seven of them.

This post puts all seven on one page: the symbol you will see in an Indian or American textbook, the boxed symbol used in European schematics, the Boolean expression, the truth table and the chip that contains it. If you would rather press buttons than read, open the logic gate simulator: tap the inputs of any gate and watch the matching truth table row light up.

Quick answerAND outputs 1 only when both inputs are 1. OR outputs 1 when at least one input is 1. NOT flips its input. XOR outputs 1 when the inputs differ. NAND, NOR and XNOR are AND, OR and XOR with the output inverted, which is what the small circle on the symbol means. A truth table with n inputs has 2ⁿ rows.

Logic gate symbols and truth tables chart: AND, OR, NOT, NAND, NOR, XOR and XNOR, each with its ANSI/IEEE distinctive shape, its IEC 60617 rectangular symbol (&, ≥1, 1, =1) and its outputs for inputs 00, 01, 10 and 11 — Figure 1. The seven gates with their ANSI and IEC symbols and the output for each input pair. Yellow outputs are 1. Open this chart in the simulator and tap a row to try that gate.

What do the logic gate symbols mean?

Two symbol sets are in common use, and a good engineer reads both.

The distinctive shapes come from the US military standard MIL-STD-806 and were formalised as ANSI/IEEE Std 91. Each function has its own outline. AND is a D shape: a flat back and a round front. OR is a pointed shield with a curved back. NOT is a triangle. XOR is the OR shield with a second curved line behind the inputs. These are the shapes in CBSE and state board textbooks, in most Arduino tutorials and in nearly every datasheet from a US manufacturer.

The rectangular symbols come from IEC 60617-12, the international standard used across Europe and in a lot of industrial documentation. Every gate is the same box, and a short label inside says what it does. The label is a counting rule about how many inputs must be 1:

& means all inputs must be 1 (AND).
≥1 means at least one input must be 1 (OR).
=1 means exactly one input must be 1 (XOR).
1 on a single-input box means a buffer, and with an output circle it is an inverter (NOT).

Both systems share one mark: a small circle, the inversion bubble. Put it on the output and the whole truth table column flips. That is the only difference between AND and NAND, OR and NOR, XOR and XNOR, and between a buffer and a NOT gate. Once you see the bubble as an instruction to flip the column, you only need to learn three rules.

What are the truth tables for all 7 gates?

A truth table lists every possible input combination and the output for each. Write the rows by counting in binary (00, 01, 10, 11) so you never skip one. Here is the full set for two-input gates:

A	B	AND	OR	NAND	NOR	XOR	XNOR
0	0	0	0	1	1	0	1
0	1	0	1	1	0	1	0
1	0	0	1	1	0	1	0
1	1	1	1	0	0	0	1

NOT has one input, so its table has two rows: 0 gives 1 and 1 gives 0.

Read the columns as four-digit codes and the inverted pairs jump out. AND is 0001 and NAND is 1110. OR is 0111 and NOR is 1000. XOR is 0110 and XNOR is 1001. Each pair is the same code with every digit flipped.

AND gate with inputs A = 1 and B = 1 lighting the output lamp, the AND truth table with the 1 1 row highlighted giving Y = 1, the 74HC08 quad AND chip pinout and the IEC & symbol — Figure 2. An AND gate with both inputs at 1. The highlighted row of the truth table is the one the inputs select, and the 74HC08 below it holds four of these gates. Open this setup in the simulator.

How to write the Boolean expressions

Boolean algebra gives each gate a short formula. AND is written as a product, $Y = A \cdot B$ , because multiplying 0s and 1s gives 1 only when both are 1. OR is written as a sum, $Y = A + B$ , with the understanding that 1 + 1 is still 1. XOR has its own circled plus, $Y = A \oplus B$ . A bar over an expression inverts it:

\begin{aligned} \text{NAND: } Y &= \overline{A \cdot B} \\ \text{NOR: } Y &= \overline{A + B} \\ \text{XNOR: } Y &= \overline{A \oplus B} \end{aligned}

A common slip is to read $\overline{A \cdot B}$ as $\overline{A} \cdot \overline{B}$ . They are different gates. The first is NAND, which is 0 only for inputs 11. The second is NOR, which is 1 only for inputs 00. De Morgan's laws connect them: $\overline{A \cdot B} = \overline{A} + \overline{B}$ . Breaking the bar changes the operator.

How many rows does a truth table need?

Each input can be 0 or 1, and every extra input doubles the number of combinations. For n inputs:

\text{rows} = 2^{n}

Worked example: a three-input alarm. A car alarm sounds when the system is armed (A), and either a door is open (B) or the bonnet is open (C). Three inputs give

2^3 = 8

rows. The rule is

Y = A \cdot (B + C)

. Going row by row: all four rows with A = 0 give 0. With A = 1, only the row B = 0, C = 0 gives 0, and the other three give 1. So the alarm sounds in 3 of the 8 cases. In gates that is one OR (for B + C) feeding one AND (with A).

The simulator's builder mode does exactly this kind of chain: the first gate combines A and B into X, the second combines X with C, and the 8-row table updates as you change either gate.

Why is XOR different from OR?

The two tables differ in a single row, inputs 11. OR says 1, XOR says 0. That row matters more than it looks.

Think of a staircase light with a switch at the bottom and another at the top. Flipping either switch must change the light, whatever the other switch is doing. That is XOR: the output is 1 when the switches disagree. If the wiring followed OR, then once both switches were on, flipping one would leave the light on and you would be stuck.

XOR gate with A = 1 and B = 0 giving Y = 1 because the inputs differ, its truth table with outputs 0, 1, 1, 0 and the 74HC86 quad XOR chip pinout — Figure 3. XOR with A = 1 and B = 0. The output is 1 because the inputs differ. Tap B to 1 and the output drops to 0, the one row where XOR and OR disagree. Open this setup in the simulator.

XOR is also a controllable inverter. With B = 0 the output equals A. With B = 1 the output is NOT A. That property puts XOR at the heart of parity checks, CRC error detection, simple stream ciphers and, most importantly, binary addition.

How do logic gates add numbers?

Add two single bits and there are four cases. 0 + 0 = 0, 0 + 1 = 1, 1 + 0 = 1 and 1 + 1 = 2, which is 10 in binary. Write the answer as two digits, a carry and a sum:

A	B	Carry	Sum
0	0	0	0
0	1	0	1
1	0	0	1
1	1	1	0

The sum column is 0110, the XOR column. The carry column is 0001, the AND column. So one XOR and one AND add two bits. That circuit is the half adder.

Half adder circuit built from one XOR and one AND gate adding 1 + 1: sum 0, carry 1, so the answer is 10 in binary, which is 2, with the half adder truth table — Figure 4. A half adder adding 1 + 1. The XOR gives the sum bit 0, the AND gives the carry 1, so the answer reads 10 in binary. Open this setup in the simulator.

A half adder cannot accept a carry from the column to its right, so it can only handle the lowest bit. The full adder fixes that. It is two half adders and an OR gate: the first XOR makes $P = A \oplus B$ , the second XOR adds the incoming carry, and the carry out is 1 if either AND gate fires.

\begin{aligned} S &= A \oplus B \oplus C_{\text{in}} \\ C_{\text{out}} &= (A \cdot B) + \big((A \oplus B) \cdot C_{\text{in}}\big) \end{aligned}

Full adder circuit from two XOR gates, two AND gates and an OR gate with A, B and carry in all 1, giving sum 1 and carry out 1 (11 in binary = 3), and the 8 row full adder truth table — Figure 5. A full adder with all three inputs at 1. The answer is 11 in binary, which is 3. Five gates, eight rows. Open this setup in the simulator.

Worked example: 5 + 3 with four full adders. In binary, 5 is 0101 and 3 is 0011. Start at the right with no carry in.
Bit 0: 1 + 1 + 0 = 10, so sum 0, carry 1.
Bit 1: 0 + 1 + 1 = 10, so sum 0, carry 1.
Bit 2: 1 + 0 + 1 = 10, so sum 0, carry 1.
Bit 3: 0 + 0 + 1 = 01, so sum 1, carry 0.
Reading the sums from bit 3 down gives 1000, which is 8. Each line is one row of the full adder truth table, and you can check every one in the simulator by setting A, B and Cin.

How fast is a gate adder?

The carry has to pass through each full adder in turn, so a long adder waits for it. On the carry path each bit adds roughly two gate delays (an AND then the OR). The TI SN74HC00 datasheet gives a typical propagation delay of 9 ns at 4.5 V and a maximum of 18 ns at 25 °C.

Worked example: ripple time. 8 bits × 2 gates per bit × 9 ns = 144 ns typical for an 8-bit ripple adder built from 74HC parts. A 32-bit version takes 32 × 2 × 9 ns = 576 ns, which caps it near 1.7 million additions per second. A processor adder finishes the same job in well under a nanosecond because it uses faster on-chip transistors and carry-lookahead logic that works out the carries in parallel instead of waiting for each one.

Why are NAND and NOR called universal gates?

Any truth table you can write can be built from NAND gates alone. Tie both inputs of a NAND together and it becomes NOT. Follow a NAND with that NOT and you have AND. Put NOTs on the inputs of a NAND and De Morgan's law turns it into OR. The minimum counts using two-input NAND gates are:

Gate	NAND gates needed
NOT	1
AND	2
OR	3
NOR	4
XOR	4
XNOR	5

Two NAND gates in series with the second input held at 1: the second NAND acts as an inverter so the output Y follows A AND B, shown with an 8 row truth table — Figure 6. Two NANDs with the second one's spare input held at 1. The second NAND inverts, so Y follows A AND B. Open this setup in the simulator.

Here is the misconception worth correcting. Many students picture a NAND chip as an AND gate with a NOT bolted on. In CMOS it is the other way round. A two-input CMOS NAND needs four transistors: two P-channel in parallel and two N-channel in series. An AND gate is built as that NAND followed by a two-transistor inverter, six transistors in all. NAND is the cheaper, faster, natural gate, and AND is the derived one.

Which chip has which gate?

On a breadboard you will use the 7400 family. The 74HC versions are CMOS, run from 2 V to 6 V and come in a 14-pin package with ground on pin 7 and VCC on pin 14.

Function	Part	Gates per chip
NAND	74HC00	4
NOR	74HC02	4
NOT	74HC04	6
AND	74HC08	4
OR	74HC32	4
XOR	74HC86	4
XNOR	74HC7266	4

Two traps catch beginners. First, the 7402 NOR has a different pinout from the 7400, 7408, 7432 and 7486: each NOR output comes first in its group of three pins (1Y on pin 1), so a NOR chip dropped into a NAND layout drives its outputs against your inputs. The simulator draws each chip's real pin labels so you can check. Second, the older 74LS266 XNOR has open-collector outputs that need a pull-up resistor. The pull-up resistor guide shows how to size one.

Voltage levels are the other thing a truth table hides. A 74HC gate at 4.5 V reads anything above 3.15 V as 1 and anything below 1.35 V as 0. Those are 70 percent and 30 percent of the supply. At 5 V the same ratio puts the HIGH threshold near 3.5 V, which a 3.3 V microcontroller output does not reach. That is why a 3.3 V board driving a 5 V 74HC chip needs a 74HCT part or a level shifter, as the 3.3 V to 5 V level shifter post explains. If you are moving on to chips with memory, the 74HC595 shift register guide is the natural next step.

Try it yourself

Open the full adder in the simulator and walk through all eight rows by tapping A, B and Cin. Then switch to the builder, pick NAND for both gates and hold C at 1: you will have proved NAND is universal with your own fingers. When you want a reference sheet, the symbols chart preset draws the whole set at once.

Sources

Texas Instruments SN74HC00 quad 2-input NAND gate datasheet: supply range, VIH and VIL at 4.5 V, propagation delay, pinout.
Texas Instruments SN74HC02 quad 2-input NOR gate datasheet: the NOR pinout with outputs on pins 1, 4, 10 and 13.
Texas Instruments CD74HC7266 quad XNOR product page
IEC 60617 graphical symbols database, threshold and OR elements
Logic gate, Wikipedia: ANSI/IEEE Std 91 and MIL-STD-806 symbol history
All About Circuits: CMOS gate circuitry (NAND and AND transistor structure)

Frequently asked questions

What are the 7 basic logic gates and their symbols?

AND (a D shape), OR (a curved shield), NOT (a triangle with a small circle), NAND (the AND shape with a circle), NOR (the OR shape with a circle), XOR (the OR shape with an extra curved line at the inputs) and XNOR (the XOR shape with a circle). In IEC 60617 they are all rectangles labelled &, ≥1, 1 and =1, with a circle on the output for the inverted gates.

How do you remember logic gate truth tables?

Learn three rules and the bubble. AND is 1 only when every input is 1. OR is 1 when any input is 1. XOR is 1 when the inputs differ. A small circle on the output inverts the whole column, so NAND is AND flipped, NOR is OR flipped and XNOR is XOR flipped.

What does the small circle on a logic gate symbol mean?

It is the inversion bubble. It means the output (or an input, if the circle sits there) is inverted, so a 1 becomes 0 and a 0 becomes 1. The circle is what turns AND into NAND, OR into NOR and XOR into XNOR in both the ANSI and the IEC symbol sets.

How many rows does a truth table have for 3 inputs?

Eight. A truth table has 2 to the power of n rows for n inputs, so 2 inputs give 4 rows, 3 inputs give 8 rows and 4 inputs give 16 rows. List them by counting in binary from 000 to 111 and you will never miss one.

Which 7400 series chip is which gate?

7400 is quad 2-input NAND, 7402 is quad 2-input NOR, 7404 is the hex inverter (NOT), 7408 is quad 2-input AND, 7432 is quad 2-input OR and 7486 is quad 2-input XOR. A common XNOR in CMOS is the 74HC7266. Watch the 7402: its pinout differs from the others.